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Named-Input Adder
Adds two signals resolved entirely by user-typed names (no input ports, no input wires) and publishes the sum under a third user-typed name (no output port, no output wires either). Inputs and output are declared exclusively as named_inputs[] / named_outputs[] — the only way to drive in_a / in_b or consume out is by typing a published signal name. Both inputs are 1-step delayed by construction via the named-input pipeline (no algebraic-loop / topo-order coupling). The output is a regular C++ slot the planner allocates as a singleton (no ComponentGraphEdge); other components reach it by name through the same registry as a GoTo block, and the value also lands in results.csv whenever the user fills in out_name.
Category: Math
Keywords: +, Σ, sum, addition, named, wireless, goto, from, label, signal
Ports
This component has no wired ports — see Named inputs / outputs below if any.
Parameters
| Name | Label | Type | Default | Units | Description |
|---|---|---|---|---|---|
in_a_name | Input A name | string | (empty) | — | Name of the published signal driving `in_a`. Matches a `GoTo` `output_name`, a labeled wire `signal_name`, or another component's observable `name_param`. Always 1-step delayed. Leave empty to read 0. |
in_b_name | Input B name | string | (empty) | — | Name of the published signal driving `in_b`. Same resolution rules as Input A. Always 1-step delayed. |
out_name | Output name | string | (empty) | — | Name under which the sum is published into the named-signal registry. Other components can resolve this name via their own `named_inputs` parameters or via a `From` block; the value also lands in `results.csv` whenever this field is non-empty. Leave empty to disable publication (the C++ slot still exists, it just has no addressable name). |
Used in samples
Implemented in C++ class SimCompCtlNamedInputAdder (components/control/CSim_comp_ctl_named_input_adder/sim_comp_ctl_named_input_adder.h).