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Clock
Periodic 0/1 square-wave generator with configurable frequency, duty cycle and phase. Drives flip-flops and other sequential digital logic.
Category: Digital Logic / Sequential
Keywords: CLK, clk, edge, trigger, square wave, digital, timing, pulse
Ports
| Name | Direction | Value type | Notes |
|---|---|---|---|
out | output | int |
Parameters
| Name | Label | Type | Default | Units | Description |
|---|---|---|---|---|---|
frequency | f (Hz) | double | 1 | — | Square-wave frequency. The output toggles between 0 and 1 with period 1/f. |
duty | Duty | double | 0.5 | — | Fraction of the period the output is high (1). 0.5 = symmetric square wave; 0.25 = 25% duty cycle (high for 1/(4f) seconds, low for 3/(4f) seconds). Clamped to [0, 1]. |
phase | Phase | double | 0 | — | Phase offset as a fraction of the period (0..1). Use to stagger multiple clocks driving different flip-flops. |
Implemented in C++ class SimCompCtlClock (components/control/CSim_comp_ctl_clock/sim_comp_ctl_clock.h).